The present disclosure relates to semiconductor structures, and particularly to complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) including gate spacers of the same thickness and a method of manufacturing the same.
A CMOS circuit includes p-type transistors and n-type transistors. If a process integration scheme employing two separate epitaxial deposition processes are employed to form the raised active regions of the p-type transistors and the raised active regions of the n-type transistors, one type of transistors needs to be covered with a dielectric layer while a selective epitaxy process is performed on physically exposed semiconductor surfaces of the other type of transistors. The inherent asymmetry in the dielectric material stack during formation of gate spacers for the two types of transistors results in thicker gate spacers for the type of transistors on which a second selective epitaxy process is performed. The difference in the thicknesses of the gate spacers across the two types of transistors results in a difference in the extension length across the two types of transistors when epitaxial films are used for doping source and drain extension regions, which can adversely impact the device performance. In view of the deleterious effect due to the differences in the thicknesses of the gate spacers of different types of transistors, a scheme for providing the same thickness for the gate spacers of all types of transistors on a same substrate is desired.